It is often desirable to connect circuit patterns on one side of a semiconductor wafer with circuit patterns on the opposite side of the wafer. Various techniques are known for providing conductive via-holes through the wafer to provide this connection, such as by laser or electron beam drilling followed, in some methods, by a plating operation to cause the interior surface of the via-hole to be conductive.
It is also sometimes necessary to provide a heat sink on one surface of the semiconductor wafer. This can also be done by a plating operation. While it is desirable to combine as many steps of the two operations as possible, a number of obstacles exist. For example, ultrasonic agitation of the electrolyte is necessary during electrolytic plating of deep via-holes with steep side walls and small diameters in order for the plating to be uniform inside the via-hole. However, where a photoresist mask has previously been applied, as for example to define the heat sinks, the photoresist mask is likely to peel off in a short time under ultrasonic agitation.
Where a photoelectrochemical plating technique is used to fill up the via-holes as described in U.S. Pat. No. 4,399,004, followed by selective electrolytic heat sink plating using a photoresist mask, there is the problem that photoelectrochemical plating is very sensitive to the surface finish of the via-holes and the wafer and can be difficult to control under production conditions.
Thus, there is a need for a process for simply and simultaneously forming plated via-holes and heat sinks.